Advanced Technologies and Reliable Design for Nanotechnology Systems

328 0740-7475/05/$20.00 © 2005 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers THERE IS RENEWED INTEREST in using hardware redundancy to mask faulty behavior in nanoelectronic components. In this article, we go back to the early ideas of von Neumann and review the key concepts behind Ntuple modular redundancy (NMR), hardware multiplexing, and interwoven redundant logic. We discuss several important concepts for redundant nanoelectronic system designs based on recent results. First, we use Markov chain models to describe the error-correcting and stationary characteristics of multiple-stage multiplexing systems. Second, we show how to obtain the fundamental error bounds by using bifurcation analysis based on probabilistic models of unreliable gates. Third, we describe the notion of random interwoven redundancy. Finally, we compare the reliabilities of quadded and random interwoven structures by using a simulation-based approach. We observe that the deeper a circuit’s logical depth, the more fault-tolerant the circuit tends to be for a fixed number of faults. For a constant gate failure rate, a circuit’s reliability tends to reach a stationary state as its logical depth increases. Two widely studied fault tolerance techniques that use hardware redundancy to mask faults are NMR and the multiplexed logic approach. The multiplexed logic approach, motivated by the pioneering work of John von Neumann, began as an attempt to build early digital computers out of unreliable components.1 This approach and subsequent derivatives2-6 have provided insight on how to design reliable nanoelectronic systems out of components that might fundamentally be less reliable than those of currently available technologies.7,8 Quantum effects, increased sensitivity to noise, and decreased fabrication tolerances inherent in nanoelectronics will all contribute to reliability losses. Hence, questions arise as to what are the error behaviors of a fault-tolerant system, and what are the maximal error rates beyond which no reliable designs are possible. With these understandings, new questions arise: Are there new fault-tolerant designs that are well-suited for nanoelectronics? If so, what are the characteristics of these designs in contrast with theoretical models? To address the first set of questions, we use a Markov chain model to analyze a multiplexing system to infer how system reliability depends on individual gate reliabilities. We then use bifurcation analysis of expressions describing logic circuit behavior that account for the probability of gate errors. To address the latter questions, we use interwoven redundant logic with randomized connectivity to cope with, and even leverage, the potential randomness of nanoscale interconnects resulting from either failures or the random characteristics of self-assembly. We then use simulations to experimentally investigate the system behaviors of random Toward HardwareRedundant, Fault-Tolerant Logic for Nanoelectronics